The present disclosure relates to semiconductor integrated circuit manufacturing, and more specifically to optimizing mask assist features for a lithographic mask for printing a silicon wafer design layout layer.
Photolithographic masks are used to fabricate semiconductor devices such as integrated circuits. The masks are patterned according to the images that are to be printed on a silicon wafer, for example. Light is transmitted through the openings in the mask and focused onto a photoresist layer that has been coated on the silicon wafer. The transmitted and focused light exposes portions of the photoresist. A developer is used to remove either the exposed portions or the unexposed portions of the resist layer, depending on whether the photoresist is a positive or negative type resist. The remaining photoresist serves to protect the underlying layer during further processing of the wafer (e.g., etching exposed portions of the underlying layer, implanting ions into the wafer, etc.). After the wafer fabrication process for this pattern is performed, the remaining portion of the photoresist layer can be removed from the underlying substrate. The pattern that is printed onto the photoresist correlates with that of the photolithographic mask.
There is a continuing objective to increase the density with which various integrated circuit structures are arranged. As technology nodes decrease, the critical dimension of the features to be printed on the silicon wafer is reduced. As the size of the features becomes smaller than the wavelength of light, distortions occur in the printed patterns. To reduce these distortions, mask assist features (AF) are added to the mask between the features to be printed. AF are not printed on the semiconductor wafer, but help to balance the optical density of the feature pattern.
AF are special geometrical figures, or polygons, which are added (or sometimes subtracted) to design layouts in lithographic processes for manufacturing integrated circuits and other related fields such as hard-disk heads, etc. AF are also referred to as sub-resolution assist features (SRAF), scatter bars (SB), and in some cases printable assist features (PRAF), but the more general term, AF, will be used throughout this disclosure. Given a design layout representing a circuital layer, AF figures are created with specified dimensions (widths, heights, etc.) and at specified distances (placements relative to the main features of the circuit). The number of AF per given layout feature, the set of AF dimensions, and the distances from the main features are collectively referred to as the AF rules set.
AF improve process latitude, or the change in critical dimension for a given change in exposure dose. For a given target pattern, if chosen properly, the AF balance the optical density such that the variation in intensity across the features to be printed is reduced. The parameter values in an AF rules set depend on several technology and process conditions. For example, the critical dimensions (CD) of the layout features, lithography wavelength and illumination, and mask type all affect the parameter values. Identifying optimal parameter values in an AF rules set (or optimal AF rules, for short) is a fundamental problem in process technology development for semiconductor manufacturing.
Currently, AF generation is performed by using a combination of lithographic simulations and silicon verification with test masks and test chips, from which AF rules are derived. A set of layout geometrical configurations (typically one dimensional lines and space structures of different sizes and pitches) is selected, and then a large combinatorial set of AF numbers, widths, and distances are evaluated by lithographic simulations, followed by validation of mask fabrication constraints. Various objective functions are used for this evaluation based on manufacturability metrics (for instance, normalized image log slope, focus and exposure latitude, etc.). Experimental verification on silicon is often used on a subset of candidate AF rules values. This process is cumbersome, computationally very expensive, and error-prone, which often results in a set of sub-optimal rules.
As the technology node and target feature CD are reduced, the complexity of the AF rules optimization increases. A need therefore exists for a more accurate AF generation process with fewer computations.